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1 ? fn3179.3 ICL7660S super voltage converter the ICL7660S super voltage converter is a monolithic cmos voltage conversion ic that guarantees significant performance advantages over other similar devices. it is a direct replacement for the industry standard icl7660 offering an extended operating supply voltage range up to 12v, with lower supply current. no external diode is needed for the ICL7660S. in addition, a frequency boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. all improvements are highlighted in th e electrical s pecifications section. critical parameters are guaranteed over the entire commercial, industrial and military temperature ranges. the ICL7660S performs supply voltage conversion from positive to negative for an i nput range of 1.5v to 12v, resulting in complementary outp ut voltages of -1.5v to -12v. only 2 non-critical external capacitors are needed for the charge pump and charge reservoir functions. the ICL7660S can be connected to function as a voltage doubler and will generate up to 22.8v with a 12v input. it can also be used as a voltage multiplier or voltage divider. the chip contains a series dc power supply regulator, rc oscillator, voltage level translator, and four output power mos switches. the oscillator, when unloaded, oscillates at a nominal frequency of 10khz for an input supply voltage of 5.0v. this frequency can be lowered by the addition of an external capacitor to the ?osc? terminal, or the oscillator may be over-driven by an external clock. the ?lv? terminal may be tied to gnd to bypass the internal series regulator and improve low voltage (lv) operation. at medium to high voltages (3.5v to 12v), the lv pin is left floating to prevent device latchup. features ? guaranteed lower max supply current for all temperature ranges ? wide operating voltage range 1.5v to 12v ? 100% tested at 3v ? no external diode over full temperature and voltage range ? boost pin (pin 1) for higher switching frequency ? guaranteed minimum power efficiency of 96% ? improved minimum open circuit voltage conversion efficiency of 99% ? improved scr latchup protection ? simple conversion of +5v logic supply to 5v supplies ? simple voltage multiplication v out = (-)nv in ? easy to use - requires only 2 external non-critical passive components ? improved direct replacement for industry standard icl7660 and other second source devices ? available in lead free applications ? simple conversion of +5v to 5v supplies ? voltage multiplication v out = nv in ? negative supplies for data acquisition systems and instrumentation ? rs232 power supplies ? supply splitter, v out = v s /2 pinouts ICL7660S (pdip, soic) top view ICL7660S (can) top view boost cap+ gnd cap- 1 2 3 4 8 7 6 5 v+ osc lv v out v+ (and case) lv cap+ cap- boost gnd osc v out 2 4 6 1 3 7 5 8 ordering information part # temp. range ( o c) package pkg. dwg. # ICL7660Scba 0 to 70 8 ld soic (n) m8.15 ICL7660Scpa 0 to 70 8 ld pdip e8.3 ICL7660Siba -40 to 85 8 ld soic (n) m8.15 ICL7660Sibaz (note 1) -40 to 85 8 ld soic (n) (lead-free) m8.15 ICL7660Sibazt (note 1) -40 to 85 8 ld soic (n) (lead-free) tape and reel m8.15 ICL7660Sipa -40 to 85 8 ld pdip e8.3 ICL7660Smtv (note 2) -55 to 125 8 pin metal can t8.c notes: 1. intersil lead free products employ special lead free material sets; molding compounds / die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and lead free soldering operations. intersil lead free products are msl classified at lead free peak reflow temperatures that meet or exceed the lead free requirements of ipc/jedec j std-020b. 2. add /883b to part number if 883b processing is required. data sheet january 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute maximum rati ngs thermal information supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0v lv and osc input voltage (note 3) v+ < 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v+ + 0.3v v+ > 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ -5.5v to v+ +0.3v current into lv (note 3) v+ > 3.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 a output short duration v supply 5.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous storage temperature range . . . . . . . . . . . . . . . . . . -65 o c to 150 o c operating conditions temperature range ICL7660Sm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c ICL7660Si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c ICL7660Sc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 4) ja ( o c/w) jc ( o c/w) pdip. . . . . . . . . . . . . . . . . . . . . . . . . . . 110 n/a plastic soic. . . . . . . . . . . . . . . . . . . . . 160 n/a metal can. . . . . . . . . . . . . . . . . . . . . . . 160 70 maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. connecting any terminal to voltages greater than v+ or less than gnd may cause destructive latchup. it is recommended that no inputs from sources operating from external supplies be applied prior to ?power up? of ICL7660S. 4. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications v+ = 5v, t a = 25 o c, osc = free running, test circuit figure 12, unless otherwise specified parameter symbol test conditions min typ max units supply current (note 7) i+ r l = , 25 o c - 80 160 a 0 o c < t a < +70 o c - - 180 a -40 o c < t a < 85 o c - - 180 a -55 o c < t a < 125 o c - - 200 a supply voltage range - high (note 8) v+ h r l = 10k, lv open, t min < t a < t max 3.0 - 12 v supply voltage range - low v+ l r l = 10k, lv to gnd, t min < t a < t max 1.5 - 3.5 v output source resistance r out i out = 20ma - 60 100 ? i out = 20ma, 0 o c < t a < 70 o c - - 120 ? i out = 20ma, -25 o c < t a < 85 o c - - 120 ? i out = 20ma, -55 o c < t a < 125 o c - - 150 ? i out = 3ma, v+ = 2v, lv = gnd, 0 o c < t a < 70 o c - - 250 ? i out = 3ma, v+ = 2v, lv = gnd, -40 o c < t a < 85 o c - - 300 ? i out = 3ma, v+ = 2v, lv = gnd, -55 o c < t a < 125 o c - - 400 ? oscillator frequency (note 7) f osc c osc = 0, pin 1 open or gnd 5 10 - khz c osc = 0, pin 1 = v+ - 35 - khz power efficiency p eff r l = 5k ? 96 98 - % t min < t a < t max r l = 5k ? 95 97 - - voltage conversion efficiency v out eff r l = 99 99.9 - % ICL7660S
3 oscillator impedance z osc v+ = 2v - 1 - m ? v+ = 5v - 100 - k ? notes: 5. derate linearly above 50 o c by 5.5mw/ o c 6. in the test circuit, there is no exte rnal capacitor applied to pin 7. however, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, of the order of 5pf. 7. the intersil ICL7660S can operate without an external diode over the full temperat ure and voltage range. this device will fun ction in existing designs which incorporate an external diode with no degradation in overall circuit performance. 8. all significant improvements over t he industry standard icl7660 are highlighted. electrical specifications v+ = 5v, t a = 25 o c, osc = free running, test circuit figure 12, unless otherwise specified (continued) parameter symbol test conditions min typ max units typical performance curves (test circuit figure 12) figure 1. operating voltage as a function of temperature figure 2. output source resistance as a function of supply voltage figure 3. output source resistance as a function of temperature figure 4. power conversion efficiency as a function of oscillator frequency -55 -25 0 25 50 100 125 12 10 8 6 4 2 0 supply voltage (v) temperature ( o c) supply voltage range (no diode required) 250 200 150 100 50 0 02 4681012 supply voltage (v) output source resistance ( ? ) t a = 125 o c t a = 25 o c t a = -55 o c 350 300 250 200 150 100 50 0 output source resistance ( ? ) -50 -25 0 25 50 75 100 125 temperature ( o c) i out = 20ma, v+ = 12v i out = 20ma, v+ = 5v i out = 20ma, v+ = 5v i out = 3ma, v+ = 2v 98 96 94 92 90 88 86 84 82 80 power conversion efficiency (%) 100 1k 10k 50k osc frequency f osc (hz) v+ = 5v t a = 25 o c i out = 1ma ICL7660S
4 figure 5. frequency of oscillation as a function of external oscillator capacitance figure 6. unloaded oscillator frequency as a function of temperature figure 7. output voltage as a function of output current figure 8. supply current and power conversion efficiency as a function of load current figure 9. output voltage as a function of output current figure 10. supply current and power conversion efficiency as a function of load current typical performance curves (test circuit figure 12) (continued) 1 10 100 1k oscillator frequency f osc (khz) 10 9 8 7 6 5 4 3 2 1 0 c osc (pf) v+ = 5v t a = 25 o c oscillator frequency f osc (khz) 20 18 16 14 12 10 8 -55 -25 0 25 50 75 100 125 temperature ( o c) v+ = 10v v+ = 5v output voltage (v) 1 0 -1 -2 -3 -4 -5 010203040 load current (ma) v+ = 5v t a = 25 o c power conversion efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 100 90 80 70 60 50 40 30 20 10 0 load current (ma) 01020 30 40 5060 v+ = 5v t a = 25 o c supply current (ma) output voltage (v) 2 1 0 -1 -2 012 345 6789 load current (ma) t a = 25 o c v+ = 2v 100 90 80 70 60 50 40 30 20 10 0 16 14 12 10 8 6 4 2 0 0 1.5 3 4.5 6 7.5 9 load current (ma) v+ = 2v t a = 25 o c power conversion efficiency (%) supply current (ma) (note 9) ICL7660S
5 detailed description the ICL7660S contains all the necessary circuitry to complete a negative voltage conv erter, with the exception of 2 external capacitors which may be inexpensive 10 f polarized electrolytic types. th e mode of operation of the device may be best understood by considering figure 13, which shows an idealized negative voltage converter. capacitor c 1 is charged to a voltage, v+, for the half cycle when switches s 1 and s 3 are closed. (note: switches s 2 and s 4 are open during this half cycle.) during the second half cycle of operat ion, switches s 2 and s 4 are closed, with s 1 and s 3 open, thereby shifting capacitor c 1 to c 2 such that the voltage on c 2 is exactly v+, assuming ideal switches and no load on c 2 . the ICL7660S approaches this ideal situation more closely than existing non-mechanical circuits. in the ICL7660S, the 4 switches of figure 13 are mos power switches; s 1 is a p-channel devices and s 2 , s 3 and s 4 are n-channel devices. the main difficulty with this approach is that in integrating the switches, the substrates of s 3 and s 4 must always remain reverse biased with respect to their sources, but not so much as to degrade their ?on? resistances. in addition, at ci rcuit start up, and under output short circuit conditions (v out = v+), the output voltage must be sensed and the substrate bias adjusted accordingly. failure to accomplish this would result in high power losses and probable device latchup. this problem is eliminated in the ICL7660S by a logic network which senses the output voltage (v out ) together with the level translators, and switch es the substrates of s 3 and s 4 to the correct level to maintain necessary reverse bias. the voltage regulator portion of the ICL7660S is an integral part of the anti-latchup circuitr y, however its inherent voltage drop can degrade operation at low voltages. therefore, to improve low voltage operation ?lv? pin should be connected to gnd, disabling the regulator. for supply voltages greater than 3.5v the lv terminal must be left open to insure latchup proof operation, and prevent device damage. theoretical power efficiency considerations in theory a voltage converter can approach 100% efficiency if certain conditions are met: 1. the drive circuitry consumes minimal power. 2. the output switches have ex tremely low on resistance and virtually no offset. 3. the impedance of the pump and reservoir capacitors are negligible at the pump frequency. figure 11. output source resistance as a function of oscillator frequency note: 9. these curves include in the supply current that current fed directly into the load r l from the v+ (see figure 12). thus, approximately half the supply current goes directly to the positive side of the l oad, and the other half, through the ICL7660S, to the negative side o f the load. ideally, v out 2v in , i s 2i l , so v in x i s v out x i l . typical performance curves (test circuit figure 12) (continued) output resistance ( ? ) 400 300 200 100 0 100 1k 10k 100k oscillator frequency (hz) v+ = 5v t a = 25 o c i = 10ma c 1 = c 2 = 10 f c 1 = c 2 = 1 f c 1 = c 2 = 100 f 1 2 3 4 8 7 6 5 + - c 1 10 f i s v+ (+5v) i l r l - v out c 2 10 f ICL7660S v+ + - note: for large values of c osc (>1000pf) the values of c 1 and c 2 should be increased to 100 f. figure 12. ICL7660S test circuit ICL7660S
6 the ICL7660S approaches th ese conditions for negative voltage conversion if large values of c 1 and c 2 are used. energy is lost only in the transfer of charge between capacitors if a change in voltage occurs . the energy lost is defined by: e = 1 / 2 c 1 (v 1 2 - v 2 2 ) where v 1 and v 2 are the voltages on c 1 during the pump and transfer cycles. if the impedances of c 1 and c 2 are relatively high at the pump frequency (refer to figure 13) compared to the value of r l , there will be substantial difference in the voltages v 1 and v 2 . therefore it is not only desirable to make c 2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for c 1 in order to achieve maximum efficiency of operation. do?s and don?ts 1. do not exceed maximum supply voltages. 2. do not connect lv terminal to gnd for supply voltage greater than 3.5v. 3. do not short circuit the output to v + supply for supply voltages above 5.5v for extended periods, however, transient conditions including start-up are okay. 4. when using polarized capacitors, the + terminal of c 1 must be connected to pin 2 of the ICL7660S and the + terminal of c 2 must be connected to gnd. 5. if the voltage supply driving the ICL7660S has a large source impedance (25 ? - 30 ? ), then a 2.2 f capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2v/ s. 6. user should insure that th e output (pin 5) does not go more positive than gnd (pin 3). device latch up will occur under these conditions. a 1n914 or similar diode placed in parallel with c 2 will prevent the device from latching up under these conditions. (anode pin 5, cathode pin 3). typical applications simple negative voltage converter the majority of applications will undoubtedly utilize the ICL7660S for generation of negative supply voltages. figure 14 shows typical connections to provide a negative supply where a positive supply of +1.5v to +12v is available. keep in mind that pin 6 (lv) is tied to the supply negative (gnd) for supply voltage below 3.5v. the output characteristics of t he circuit in figure 14 can be approximated by an ideal voltage source in series with a resistance as shown in figure 14b. the voltage source has a value of -(v+). the output impedance (r o ) is a function of the on resistance of the inte rnal mos switches (shown in figure 13), the switching frequency, the value of c 1 and c 2 , and the esr (equivalent series resistance) of c 1 and c 2 . a good first order approximation for r o is: combining the four r swx terms as r sw , we see that: r sw , the total switch resistanc e, is a function of supply voltage and temperature (see the output source resistance graphs), typically 23 ? at 25 o c and 5v. careful selection of c 1 and c 2 will reduce the remaining terms, minimizing the output impedance. high value capac itors will reduce the 1/(f pump x c 1 ) component, and low esr c apacitors will lower the esr term. increasing the oscilla tor frequency will reduce the 1/(f pump x c 1 ) term, but may have the side effect of a net v out = - v in c 2 v in c 1 s 3 s 4 s 1 s 2 8 2 4 33 5 7 figure 13. idealized negative voltage converter r o ? 2(r sw1 + r sw3 + esr c1 ) + 2(r sw2 + r sw 4 + esr c1 ) + 1 + esr c2 f pump x c 1 (f pump = f osc ,r swx = mosfet switch resistance) 2 r o ? 2 x r sw + 1 + 4 x esr c1 + esr c2 ? f pump x c 1 1 2 3 4 8 7 6 5 + - 10 f 10 f ICL7660S v out = - v+ v+ + - r o v out v+ + - 14a. 14b. figure 14. simple negative converter and its output equivalent ICL7660S
7 increase in output impedance when c 1 > 10 f and is not long enough to fully charge the capacito rs every cycle. in a typical application where f osc = 10khz and c = c 1 = c 2 = 10 f: since the esrs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/f pump x c 1 ) term, rendering an increase in switching fr equency or filter capacitance ineffective. typical electrolytic capacitors may have esrs as high as 10 ? . output ripple esr also affects the ripple vo ltage seen at the output. the total ripple is determined by 2 voltages, a and b, as shown in figure 15. segment a is the vo ltage drop across the esr of c 2 at the instant it goes from being charged by c 1 (current flowing into c 2 ) to being discharged through the load (current flowing out of c 2 ). the magnitude of this current change is 2 x i out , hence the total drop is 2 x i out x esr c2 v. segment b is the voltage change across c 2 during time t 2 , the half of the cycle when c 2 supplies current the load. the drop at b is i out x t 2 /c 2 v. the peak-to-peak ripple voltage is the sum of these voltage drops: again, a low esr capacitor will result in a higher performance output. paralleling devices any number of ICL7660S voltage converters may be paralleled to reduce output resistance. the reservoir capacitor, c 2 , serves all devices while each device requires its own pump capacitor, c 1 . the resultant output resistance would be approximately: cascading devices the ICL7660S may be cascaded as shown to produce larger negative multiplication of the in itial supply voltage. however, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. the output voltage is defined by: v out = -n(v in ), where n is an integer representing the number of devices cascaded. the resulting output resistance would be approximately the weighted sum of the individual ICL7660S r out values. changing the ICL7660S oscillator frequency it may be desirable in some applications, due to noise or other considerations, to alter the oscillator frequency. this can be achieved simply by one of several methods described below. by connecting the boost pin (pin 1) to v+, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increased by approximately 3 1 / 2 times. the result is a decr ease in the output impedance and ripple. this is of major importance for surface mount applications where capacitor size and cost are critical. smaller capacitors, e.g. 0.1 f, can be used in conjunction with the boost pin in order to achieve similar output currents compared to the device free running with c 1 = c 2 = 10 f or 100 f. (refer to graph of output source resistance as a function of oscillator frequency). increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in figure 18. in order to pr event device latchup, a 1k ? resistor must be used in series with t he clock output. in a situation where the designer has generated the external clock frequency using ttl logic, the addition of a 10k ? pullup resistor to v+ supply is required. note that the pump frequency with external clocking, as with internal clocking, will be 1 / 2 of the clock frequency. output transitions occur on the positive going edge of the clock. it is also possible to increase the conversion efficiency of the ICL7660S at low load levels by lowering the oscillator frequency. this reduces the switching losses, and is shown in figure 19. however, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (c 1 ) and reservoir (c 2 ) capacitors; this is overcome by increasing the values of c 1 and c 2 by the same factor that the frequency has been reduced. for example, the addition of a 100pf capacitor between pin 7 (osc and v+ will lower the oscillator frequency to 1k hz from its nominal frequency of 10khz (a multiple of 10), and thereby necessitate corresponding increase in the value of c 1 and c 2 (from 10 f to 100 f). r o ? 2 x 23 + 1 + 4 x esr c1 + esr c2 (5 x 10 3 x 10 x 10 -6 ) r o ? 46 + 20 + 5 x esr c ? r out = r out (of ICL7660S) n (number of devices) v ripple 1 2f pump c 2 ------------------------------------------- - 2 esrc 2 i out + ?? ?? ?? ?? ? 1 2 3 4 8 7 6 5 + - 10 f ICL7660S v out v+ + - 10 f v+ cmos gate 1k ? figure 15. external clocking ICL7660S
8 positive voltage doubling the ICL7660S may be employed to achieve positive voltage doubling using the circuit shown in figure 20. in this application, the pump inverter switches of the ICL7660S are used to charge c 1 to a voltage level of v+ -v f (where v+ is the supply voltage and v f is the forward voltage on c 1 plus the supply voltage (v+) is applied through diode d 2 to capacitor c 2 . the voltage thus created on c 2 becomes (2v+) - (2v f ) or twice the supply voltage minus the combined forward voltage drops of diodes d 1 and d 2 . the source impedance of the output (v out ) will depend on the output current, but for v+ = 5v and an output current of 10ma it will be approximately 60 ? . combined negative voltage conversion and positive supply doubling figure 21 combines the functions shown in figure 14 and figure 20 to provide negative voltage conversion and positive voltage doubling simultaneously. this approach would be, for example, suitable for generating +9v and -5v from an existing +5v supply. in this instance capacitors c 1 and c 3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors c2 and c 4 are pump and reservoir respectively for the doubled positive voltage. there is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the fi nite impedance of the common charge pump driver at pin 2 of the device. voltage splitting the bidirectional characteristics can also be used to split a high supply in half, as shown in figure 22. the combined load will be evenly shared between the two sides, and a high value resistor to the lv pin ensures start-up. because the switches share the load in para llel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. by using this circuit, and then the circuit of figure 17, +15v can be converted (via +7.5, and -7.5 to a nominal -15v, al though with rather high series output resistance ( 250 ? ). regulated negative voltage supply in some cases, the output impedance of the ICL7660S can be a problem, particularly if the load current varies substantially. the circuit of figure 23 can be used to overcome this by controlli ng the input voltage, via an icl7611 low-power cmos op amp, in such a way as to maintain a nearly constant out put voltage. direct feedback is inadvisable, since the icl766 0s?s output does not respond instantaneously to change in input, but only after the switching delay. the circuit shown supplies enough delay to accommodate the ICL7660S, while maintaining adequate feedback. an increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5 ? to a load of 10ma. 1 2 3 4 8 7 6 5 + - ICL7660S v out v+ + - c 2 c 1 c osc figure 16. lowering oscillator frequency 1 2 3 4 8 7 6 5 ICL7660S v+ d 1 d 2 c 1 c 2 v out = (2v+) - (2v f ) + - + - note: d 1 and d 2 can be any suitable diode. figure 17. positive voltage doubler 1 2 3 4 8 7 6 5 ICL7660S v+ d 1 d 2 c 4 v out = (2v+) - (v fd1 ) - (v fd2 ) + - c 2 + - c 3 + - v out = -v in c 1 + - figure 18. combined negative voltage converter and positive doubler 1 2 3 4 8 7 6 5 + - + - 50 f 50 f + - 50 f r l1 v out = v+ - v - 2 ICL7660S v+ v- r l2 figure 19. splitting a supply in half ICL7660S
9 other applications further information on the operation and use of the ICL7660S may be found in an051 ?principles and applications of the icl7660 cmos voltage converter?. 1 2 3 4 8 7 6 5 + - 100 f ICL7660S 100 f v out + - 10 f icl7611 + - 100 ? 50k +8v 100k 50k icl8069 56k +8v 800k 250k voltage adjust + - figure 20. regulating the output voltage 1 2 3 4 8 7 6 5 + - ICL7660S + - 10 f 16 ttl data input 15 4 10 f 13 14 12 11 +5v logic supply rs232 data output ih5142 1 3 +5v -5v figure 21. rs232 levels from a single 5v supply ICL7660S
10 ICL7660S dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
11 ICL7660S small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ICL7660S metal can packages (can) notes: 1. (all leads) ?b applies between l1 and l2. ?b1 applies between l2 and 0.500 from the reference plane. diameter is uncontrolled in l1 and beyond 0.500 from the reference plane. 2. measured from maximum diameter of the product. 3. is the basic spacing from the c enterline of the tab to terminal 1 and is the basic spacing of eac h lead or lead position (n -1 places) from , looking at the bottom of the package. 4. n is the maximum number of terminal positions. 5. dimensioning and tolerancing per ansi y14.5m - 1982. 6. controlling dimension: inch. ?b ?d2 ? e k1 k ?b1 base and seating plane f q ?d ?d1 l1 l2 reference plane l a ?b2 ?b1 base metal lead finish section a-a a a n e 1 c l 2 1 t8.c mil-std-1835 macy1-x8 (a1) 8 lead metal can package symbol inches millimeters notes min max min max a 0.165 0.185 4.19 4.70 - ?b 0.016 0.019 0.41 0.48 1 ?b1 0.016 0.021 0.41 0.53 1 ?b2 0.016 0.024 0.41 0.61 - ?d 0.335 0.375 8.51 9.40 - ?d1 0.305 0.335 7.75 8.51 - ?d2 0.110 0.160 2.79 4.06 - e 0.200 bsc 5.08 bsc - e1 0.100 bsc 2.54 bsc - f - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 l 0.500 0.750 12.70 19.05 1 l1 - 0.050 - 1.27 1 l2 0.250 - 6.35 - 1 q 0.010 0.045 0.25 1.14 - 45 o bsc 45 o bsc 3 45 o bsc 45 o bsc 3 n8 84 rev. 0 5/18/94

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